OpenVAF is a Verilog-A compiler that can be used to compiler Verilog-A compact models into machine code. The compiler is not an executable by itself and servers as the main component of other sub-projects such as

• VerilogAE: An interface between Python and Verilog-A compact models (finished)
• OSDIC: An interface between Verilog-A compact models and circuit simulators (under development)

The aim of OpenVAF is to provide a high-quality standard compliant compiler for Verilog-A. Furthermore, OpenVAF brings modern compiler construction algorithms/data structures to a field with a serious lack of such tooling.

Some highlights of OpenVAF include:

• IDE aware design
• High-quality diagnostic messages
• A linting framework (similar to rustc)
• A modular backend including data flow analysis and various state of the art compiler optimization algorithms
• Fast binary generation using LLVM
• A robust auto differentiation implementation

#Technical Documentation

A detailed description of the parts of the Verilog-A language that are supported by OpenVAF can be found here

#News & Updates

Want to keep up with the latest news on OpenVAF and its sub-projects? Subscribe to the announcement mailing list.

#Development

Interested in joining development or have technical questions/suggestions? Simply reach out to the developer mailing list. You can either use the web interface or write a mail to ~dspom/openvaf-devel@lists.sr.ht. For those interested the source code is hosted here. Patches for this project are accepted from the developer mailing list (listed above) or as a pull request in gitlab. For help sending patches to this list, please consult git-send-email.io.