Are you performing parameter extraction?Take a look at VerilogAE
Looking to compile a compact model for your simulator of choice?OSDIC is still being developed..
OpenVAF is a Verilog-A compiler that can be used to compiler Verilog-A compact models into machine code. The compiler is not an executable by itself and servers as the main component of other sub-projects such as
The aim of OpenVAF is to provide a high-quality standard compliant compiler for Verilog-A. Furthermore, OpenVAF brings modern compiler construction algorithms/data structures to a field with a serious lack of such tooling.
Some highlights of OpenVAF include:
A detailed description of the parts of the Verilog-A language that are supported by OpenVAF can be found here
Want to keep up with the latest news on OpenVAF and its sub-projects? Subscribe to the announcement mailing list.
Interested in joining development or have technical questions/suggestions? Simply reach out to the developer mailing list. You can either use the web interface or write a mail to ~email@example.com. For those interested the source code is hosted here. Patches for this project are accepted from the developer mailing list (listed above) or as a pull request in gitlab. For help sending patches to this list, please consult git-send-email.io.
commit 03285546c2db01b4d3fdde57f9e2ab790ba28c15 Author: DSPOM <firstname.lastname@example.org> Date: 2022-07-05T10:43:13+02:00 Update repo links