VerilogAE is a Verilog-A tool useful for compact model parameter extraction. VerilogAE compiles Verilog-A source files into Python native modules which offer two primary functions:

• calculating the value of any variable marked with the (*retrieve*) attribute in the Verilog-A source.
• exposing various useful information about the compiled model, such as a list of all model parameters.

VerilogAE employs state-of-the-art compiler techniques to deliver the following features:

• generated functions only contain the minimal code required to calculate a certain variable
• all parameters and branches that can influence the value of a function can be printed.
• the dependencies between model equations can be broken by inserting measured values for a sub-model, using the following Syntax: (* retrieve="input1,input2,.." *)
• full support for partial derivatives with the ddx operator

Furthermore, VerilogAE seamlessly supports numpy arrays and employs multithreading, leading to extremely fast execution time even for large amounts of data.

#Binary compatibility

VerilogAE, version 0.7.2 and above, creates wheel files that are not specific to the Python interpreter used during compilation. The wheel files can therefore be shared between multiple computers by copying them.

Note that VerilogAE compiles native Python code and therefore the resulting wheels are specific to the host architecture (eg. x86-64) and operating system.

#News & Updates

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#Technical Support

If you experience a crash, an error or want to discuss something else please do not hesitate to write a message to the mailing list. You can either use the web interface or write a mail to ~dspom/openvaf-discuss@lists.sr.ht.